View SI3000_5007466.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SI3000
VO I C E BAN D CO D E C W I T H M I C R O P H O N E / SP E A K E R DR I V E
Features
Complete voice codec solution includes the following:
! ! ! ! ! !
84 dB ADC Dynamic Range 84 dB DAC Dynamic Range 4-12 kHz Sample Rates 30 dB Microphone Pre-Amp Programmable Input Gain/ Attenuation: -36 dB to 12 dB Programmable Output Gain/ Attenuation: -36 dB to 12 dB
! ! ! ! !
!
Support for 32 Headphones 3:1 Analog Input Mixer 3.3-5.0 V Power Supply Direct Interface to DSPs Direct Connection to Si3034, Si3035, and Si3044 ISOcapTM DAA Low profile 16 Pin SOIC Package
Ordering Information: See page 30.
Applications
! !
Pin Assignments
! !
Modem Voice Channel (DSVD) Telephony
Speech Processing General Purpose Analog I/O
SI3000
SPKRR MBIAS HDST SDI SDO FSYNC MCLK SCLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SPKRL LINEO GND VA VD LINEI MIC RESET
Description
The SI3000 is a complete voice band audio codec solution that offers high integration by incorporating programmable input and output gain/ attenuation, a microphone bias circuit, handset hybrid circuit, and an output drive for 32 headphones. The SI3000 can be connected directly to the Si3034, Si3035, and Si3044 ISOcap North American and international DAA chipsets through its daisy-chaining serial interface. The device operates from a single 3.3 to 5 V power supply and is available in a 16-pin small outline package (SOIC).
Functional Block Diagram
SI3000
0/+10/+20/+30 dB MCLK SCLK FSYNC SDI SDO Digital Interface High Pass Filter MBIAS MIC ADC LINEI 0/+10/+20 dB Handset Hybrid 0/-6/-12/-18 dB Prog Gain/ Attenuator Headphone DAC Driver SPKRR SPKRL LINEO RESET 0/-6/-12/-18 dB
Prog Gain/ Attenuator
HDST
Rev. 1.1 6/00
Copyright (c) 2000 by Silicon Laboratories
SI3000-DS11
S i3 00 0
2
Rev. 1.1
SI3000 TA B L E O F CON T E N T S
Section Page
4 14 14 14 14 14 15 15 15 15 17 18 19 19 20 30 31 36
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-amp/Microphone Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Input Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Output Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speaker Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reducing Power-on Pop Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.1
3
S i3 00 0
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature SI3000 Supply Voltage, Analog SI3000 Supply Voltage, Digital
2 2,3
Symbol
TA VA VD
Test Condition
K-grade
Min1
0 3.0 3.0
Typ
25 3.3/5.0 3.3/5.0
Max1
70 5.25 5.25
Unit
C V V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 2. The digital supply, VD, and analog supply, VA, can operate from either 3.3 V or 5.0 V. The SI3000 supports interface to 3.3 V logic when operating from 3.3 V. VD must be within 0.6 V of VA. 3. The SI3000 specifications are guaranteed using the typical application circuit (including component tolerance) of Figure 13.
Table 2. DC Characteristics, VA/VD = 5 V
(VA = 5 V 5%, VD = 5 V 5%, TA = 0 to 70C for K-grade) Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Power Supply Current, Analog1 Power Supply Current, Digital2 Total Supply Current, Sleep Mode3 Notes: 1. No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz. 2. Slave mode operation, Fs = 12.5 kHz. 3. All inputs, except MCLK, are held static, and all outputs are unloaded. Symbol VIH VIL VOH VOL IL IA ID VA pin VD pin IO = -2 mA IO = 2 mA Test Condition Min 3.5 -- 3.5 -- -10 -- -- -- Typ -- -- -- -- -- 6.5 10 -- Max -- 0.8 -- 0.4 10 10 15 1.5 Unit V V V V A mA mA mA
Table 3. DC Characteristics, VA/VD = 3.3 V
(VA = 3.3 V 10%, VD = 3.3 V 10%, TA = 0C to 70C for K-grade) Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Power Supply Current, Analog Power Supply Current, Digital2 Total Supply Current, Sleep Mode
3
Symbol VIH VIL VOH VOL IL IA ID
Test Condition
Min 2.4 --
Typ -- -- -- -- -- 6 6 --
Max -- 0.8 -- 0.35 10 10 10 1.5
Unit V V V V A mA mA mA
IO = -2 mA IO = 2 mA VA pin VD pin
2.4 -- -10 -- -- --
Notes: 1. No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz. 2. Slave mode operation, Fs = 12.5 kHz. 3. All inputs, except MCLK, are held static, and all outputs are unloaded.
4
Rev. 1.1
SI3000
Table 4. AC Characteristics
(VA, VD = 5 V 5% or 3.3 V 10%, TA = 0C to 70C for K-grade) Parameter ADC Resolution ADC Dynamic Range1,2 ADC Total Harmonic Distortion VA, VD = 3.3 V 10% ADC Total Harmonic Distortion VA, VD = 5 V 5% ADC Full Scale Level (0 dB gain) ADC Programmable Input Gain ADC Input Gain Step Size ADC Freq Response5 ADC Freq Response ADC Freq Response Line In Preamp Gain Mic In Preamp Gain ADC Input Resistance ADC Input Capacitance ADC Gain Drift DAC Resolution DAC Dynamic Range1,2 DAC Total Harmonic Distortion3 VA, VD = 3.3 V 10% DACDR DACTHD VIN = 1 kHz, -6 dB VIN=1 kHz,-6 dB,LINEO,600 VIN=1 kHz,-6 dB, SPKR, 60 VIN=1 kHz,-6 dB, HDST, 600 DAC Total Harmonic Distortion3 VA, VD = 5 V 5% DACTHD VIN=1 kHz,-3 dB,LINEO,600 VIN=1 kHz,-3 dB, SPKR, 60 VIN=1 kHz,-3 dB, HDST, 600 DAC Full Scale Level (0 dB gain) DAC Programmable Output Gain VRX AT VIN = 1 kHz 0 dB Preamp Gain
5 4 3 3
Symbol
Test Condition
Min --
Typ 16 84 -80 -80 -80 -80 1 -- 1.5 33 -- -- 0/10/20 0/10/20/ 30 20 15 0.002 16 84 -76 -72 -80 -76 -72 -80 1 --
Max -- -- -62 -62 -76 -71 -- 12 -- -- 0 0 -- -- -- -- -- -- -- -60 -60 -70 -65 -65 -76 -- 12
Unit Bits dB dB
ADCDR ADCTHD
VIN = 1 kHz, -3 dB VIN = 1 kHz, -3 dB, MIC/LINEI VIN = 1 kHz, -3 dB, HDST
80 -- -- -- -- -- -36 --
ADCTHD
VIN = 1 kHz, -3 dB, MIC/LINEI VIN = 1 kHz, -3 dB, HDST
dB
VRX
Vin = 1 kHz
Vrms dB dB Hz dB dB dB dB k pF dB/C Bits dB dB
FRR FRR FRR
Low -3 dB corner 300 Hz 3400 Hz
-- -0.1 -0.2 -- -- -- -- -- -- 80 -- -- -- -- -- -- -- -36
dB
Vrms dB
Notes: 1. DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges between 4000 and 12000 Hz. 2. 0 dB setting for analog and digital attenuation/gain. 3. THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz. 4. At 0dB gain setting, 1 Vrms input corresponds to -1.5 dB of full scale digital output code. 5. These characteristics are determined by external components. See Figure 13. 6. With a 600 load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 Vrms output.
Rev. 1.1
5
S i3 00 0
Table 4. AC Characteristics (Continued)
(VA, VD = 5 V 5% or 3.3 V 10%, TA = 0C to 70C for K-grade) Parameter DAC Output Gain Step Size DAC Freq Response5 DAC Freq Response5 DAC Freq Response DAC Line Output Load Resistance DAC Line Output Load Capacitance DAC SPKR Output Load Resistance DAC Gain Drift Interchannel Isolation (Crosstalk) HDST Full Scale Level Input HDST Full Scale Level Output6 HDST Output Resistance MIC Bias Voltage MIC Power Supply Rejection Ratio Rout Vmbias PSRR DC AT VIN = 1 kHz FRR FRR FRR Low -3 dB corner 300 Hz 3400 Hz Symbol Test Condition Min -- -- -0.01 -0.2 600 -- -- -- -- -- -- -- -- -- Typ 1.5 33 -- -- -- -- 60 0.002 90 0.5 1.0 600 2.5 40 Max -- -- 0 0 -- 40 -- -- -- -- -- -- -- -- Unit dB Hz dB dB pF dB/C dB Vrms Vrms V dB
Notes: 1. DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges between 4000 and 12000 Hz. 2. 0 dB setting for analog and digital attenuation/gain. 3. THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz. 4. At 0dB gain setting, 1 Vrms input corresponds to -1.5 dB of full scale digital output code. 5. These characteristics are determined by external components. See Figure 13. 6. With a 600 load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 Vrms output.
Table 5. Absolute Maximum Ratings
Parameter DC Supply Voltage Input Current, SI3000 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Symbol VD, VA IIN VIND TA TSTG Value -0.5 to 6.0 10 -0.3 to (VD + 0.3) -10 to 100 -40 to 150 Unit V mA V C C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6
Rev. 1.1
SI3000
Table 6. Switching Characteristics--General Inputs
(VA, VD = 5 V 5% or 3.3 V 10%, TA = 70C for K-grade, CL = 20 pF)
Parameter1 Cycle Time, MCLK MCLK Duty Cycle Rise Time, MCLK Fall Time, MCLK RESET Pulse Width2
Symbol tmc tdty tr tf trl
Test Condition
Min 16.67 40 -- -- 250
Typ -- 50 -- -- --
Max -- 60 5 5 --
Unit ns % ns ns ns
Notes: 1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. 2. The minimum RESET pulse width is the greater of 5 s or 10 MCLK cycle times.
tr
tmc
tf
MCLK
VIH VIL
RESET
trl
Figure 1. General Inputs Timing Diagram
Rev. 1.1
7
S i3 00 0
Table 7. Switching Characteristics--Serial Interface
(VA, VD = 5 V 5% or 3.3 V 10%, TA = 70C for K-grade, CL = 20 pF)
Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC Delay Time, SCLK to SDO Valid Delay Time, SCLK to FSYNC Setup Time, SDI, before SCLK Hold Time, SDI, after SCLK Setup Time, FSYNC (mode 2) before MCLK Hold Time, FSYNC (mode 2) after MCLK
Symbol tc tdty td1 td2 td3 tsu th tsu th
Test Condition
Min 354 -- -- -- -- 25 20 25 20
Typ 1/256 Fs 50 -- -- -- -- -- -- --
Max -- -- 10 20 10 -- -- -- --
Unit ns % ns ns ns ns ns ns ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V
tc
SCLK
td1 td3
VOH VOL
FSYNC
(mode 0) td3
FSYNC
(mode 1)
FSYNC
(mode 2)
td2
16-bit SDO
High-Z
D15 tsu
D14
... D2 th
D1
D0
High-Z
16-bit SDI
D15
D14
... D2
D1
D0
Figure 2. Serial Interface Timing Diagram
8
Rev. 1.1
SI3000
Table 8. Digital FIR Filter Characteristics--Transmit and Receive
(VA, VD = 5 V 5% or 3.3 V 10%, Sample Rate = 8 kHz, TA = 70C for K-Grade)
Parameter Passband (3 dB, HPFD = 1) Passband (3 dB, HPFD = 0) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay
Symbol F(3 dB) F(3 dB)
Min 0 0.01 -0.1 -- -74
Typ -- -- -- 4.4 -- 12/Fs
Max 3.6 3.6 0.1 -- -- --
Unit kHz kHz dB kHz dB sec
tgd
--
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 3, 4, 5, and 6.
Table 9. Digital IIR Filter Characteristics--Transmit and Receive
(VA, VD = 5 V 5% or 3.3 V 10%, Sample Rate = 8 kHz, TA = 70C for K-Grade)
Parameter Passband (3 dB, HPFD = 1) Passband (3 dB, HPFD = 0) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay
Symbol F(3 dB) F(3 dB)
Min 0 0.01 -0.2 -- -40
Typ -- -- -- 4.4 -- 1.6/Fs
Max 3.6 3.6 0.2 -- -- --
Unit kHz kHz dB kHz dB sec
tgd
--
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10. Figures 11 and 12 show group delay versus input frequency.
Rev. 1.1
9
S i3 00 0
Attenuation - dB
Input Frequency - Hz
Attenuation - dB
Input Frequency - Hz
Figure 3. FIR Receive Filter Response
Figure 5. FIR Transmit Filter Response
Attenuation - dB
Attenuation - dB
Input Frequency - Hz
Input Frequency - Hz
Figure 4. FIR Receive Filter Passband Ripple
Figure 6. FIR Transmit Filter Passband Ripple
For Figures 3-6, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows:
F(0.1 dB) = 0.4125 Fs F(- 3 dB) = 0.45 Fs
where Fs is the sample frequency.
10
Rev. 1.1
SI3000
Attenuation - dB
Input Frequency - Hz
Attenuation - dB
Input Frequency - Hz
Figure 7. IIR Receive Filter Response
Figure 10. IIR Transmit Filter Passband Ripple
Attenuation - dB
Delay - s
Input Frequency - Hz
Input Frequency - Hz
Figure 8. IIR Receive Filter Passband Ripple
Figure 11. IIR Receive Group Delay
Attenuation - dB
Delay - s
Input Frequency - Hz
Input Frequency - Hz
Figure 9. IIR Transmit Filter Response
Rev. 1.1
Figure 12. IIR Transmit Group Delay
11
12
S i3 00 0
Rev. 1.1
Figure 13. SI3000 Typical Application Circuit
SI3000
`
Table 10. Component Values--Typical Application
Symbol C1,C3,C6,C8 C2,C4,C5,C7,C9,C10 D1 J1,J2 JP1 K1 L1,L2 R1 R2 R4 R8 R9 R11,R12 U2 Q1 Value 0.1 F, 16 V, 20% 10 F, 16 V, 20% Motorola MMBD914L Phonejack Stereo 4 Header Relay DPDT Ferrite Bead 0 , 1/4 W 5% 51 , 1/4 W 5% 10 k, 1/4 W 5% 2.2 k, 1/4 W, 5% 10 , 1/16 W, 5% 30 , 1/16 W, 5% LM317LZ PNP Transistor
Rev. 1.1
13
S i3 00 0
Functional Description
The SI3000 is a highly integrated voice bandwidth audio codec which contains a single 16-bit A/D converter and D/A converter. The analog input path contains a microphone input with selectable gain, a line level input with selectable gain, and a handset input. Each of the inputs go through a mixer prior to A/D conversion. The result of this A/D conversion is a 16-bit signed number. Following the A/D converter is a digital programmable gain amplifier. The analog output path contains a digital programmable gain amplifier feeding a single 16-bit D/A converter. The DAC output is provided to a line output, a headphone drive output, and a handset output. Control for the various functions available on the SI3000 as well as the audio data are communicated to the device over a serial interface. The SI3000 can be connected directly to the Si3035, Si3034, Si3044 in modem applications requiring a voice channel, or the device can be used as a stand-alone codec in other voice band applications. The SI3000 offers high integration, and it needs only a few low cost, discrete components as shown in Figure 13.
Pre-amp/Microphone Bias Circuit
An internal amplifier with a selectable gain of 0 dB, 10 dB, 20 dB, or 30 dB is provided for the MIC input and an internal amplifier with a selectable gain of 0 dB, 10 dB, or 20 dB, is provided for the LINEI input. AC coupling is required for both inputs because any DC offset on the input will be amplified if gain is selected. Gain settings for the LINEI and MIC inputs are achieved by writing the RX Gain Control 1 register 5. When gain is disabled, these inputs become line level inputs with a full scale input of 1 Vrms. A microphone bias circuit is provided on-chip which consists of a 2.5 V reference output capable of sourcing up to 5 mA of current. This circuit can be used for active microphones requiring a bias source.
Programmable Input Gain/Attenuation
The signals from the microphone, line, or handset inputs are mixed and then routed to the A/D converter and a digital programmable gain circuit which provides up to 12 dB of gain or -34.5 dB of attenuation in 1.5 dB steps. Level changes only take effect on zero crossings to minimize audible artifacts. The requested level change is implemented if no zero crossing is found after 256 frames. Write the ADC Volume Control register 6 to set digital input gain/attenuation.
Analog Inputs
The typical connection diagram (Figure 13) shows the recommended external analog circuitry for the SI3000. The device supports three mono analog inputs--line level, microphone level, and a handset input. Each of these inputs is provided to a mixer circuit prior to A/D conversion. Each analog input may also be muted by writing the appropriate bits in the control registers. Unused analog inputs should be tied to GND through a 0.1 F capacitor. This prevents any DC current flow.
Analog Outputs
The analog outputs of the D/A converter are routed to a line level output (LINEO), a pair of speaker outputs (SPKRL and SPKRR), and a handset. Each analog output can be independently muted.
Si3034/35/44 Chipsets
Si3021 DAA (Master) DSP SI3000 Voice Codec Si3012 DAA or Si3014 DAA or Si3015 DAA SPKR Handset Line Mic TIP RING
Discretes
Figure 14. SI3000 with Silicon Labs DAA System Diagram
14
Rev. 1.1
SI3000
Programmable Output Gain/Attenuation
Prior to D/A conversion, the SI3000 contains a digital programmable gain/attenuator which provides up to 12 dB of gain or -34.5 dB of attenuation in 1.5 dB steps. Level changes only take effect on zero crossings to minimize audible artifacts. The requested level change is implemented if no zero crossing is found after 256 frames. Write the DAC Volume Control (register 7) to set digital input gain/attenuation. pulldown resistor, and MCLK is a 256 Fs input which is internally multiplied using the on-chip phase-locked loop (PLL) to clock the A/D converter and D/A converter. In master mode, the master clock (MCLK) is an input and the serial data clock (SCLK) is an output. The MCLK frequency and the value of the sample rate control registers 3 and 4 determine the sample rate (Fs). The serial port clock, SCLK, runs at 256 bits per frame, where the frame rate is equivalent to the sample rate. Digital information is transferred between the DSP and the SI3000 in the form of 16-bit Primary Frames and 16-bit Secondary Frames. There are separate pins for receive (SDO) and transmit (SDI) functions, providing simultaneous receive/transmit operation within each frame. Primary Frames are used for digital audio data samples. Primary Frames occur at the frame rate and are always present. Secondary Frames are used for accessing internal SI3000 registers. Secondary Frames are not always present and are requested on-demand. When Secondary Frames are present, they occur mid-point between Primary Frames. Hence, no Primary Frames are dropped. On Primary Frame transmits (DSP to SI3000), the SI3000 treats the LSB (16th bit) as a flag to request a Secondary Frame. Therefore, out of 16-bits of transmit data on SDI, only 15-bits represent actual audio data. When secondary frames are not present, no transmission occurs during this time slot. On Primary Frames receives (SI3000 to DSP), the SI3000 drives SDO with 16-bits of audio data, if the SI3000 is in either Serial Mode 0 or 1. However, if the SI3000 is in SLAVE mode (Mode 2), the SI3000 supplies 15-bits of Audio Data to the DSP and always drives the LSB zero. This feature is designed to work with the Si3021 register 14 SSEL set to 10. In this system configuration, when the DSP receives Primary Frames, it can check the LSB to determine whether the receive data is from the Si3021 or from the SI3000. On Secondary Frame receives and transmits; the SI3000 treats the input and output serial stream as 16-bits of data. Figure 15 shows the relative timing of the serial frames. Figure 16 and Figure 17 illustrate the secondary frame write cycle and read cycle, respectively. During a read cycle, the R/W bit is high and the 5-bit address field contains the address of the register to be read. The contents of the 8-bit control register are placed on the SDO signal. During a write cycle, the R/W bit is low and the 5-bit address field contains the address of the register to be written. The 8-bit data to be written immediately follows the address on SDI. Only one register can be read or written during each secondary frame. See "Control Registers" on page 20 for the register addresses and functions.
15
Line Output
LINEO is a line level analog output signal centered around a common mode voltage. The minimum recommended load impedance is 600 . This output is a fully filtered output with a 1 Vrms full scale range. The only external component required is the 10 F DC blocking capacitor shown in Figure 13 on page 12. This output may be muted through the LOM bit in register 6 or attenuated by setting the analog attenuation bits in register 9.
Speaker Output
The SPKRL and SPKRR analog outputs are capable of driving a small loudspeaker whose impedance is typically 32 (see Figure 13 on page 12). The speaker outputs may be muted through the SLM and SRM bits in the DAC Gain Control register 7 or attenuated by setting the analog attenuation bits in register 9.
Digital Interface
The SI3000 has two serial interface modes that support most standard modem DSPs. These modes are selected by the addition of a 50 k pull-down/up resistor on the SDO and SCLK pins as shown in Figure 13 on page 12. To determine the mode, the SI3000 reads SDO and SCLK on the first rising edge of MCLK after RESET goes low. The key difference between these two serial modes is the operation of the FSYNC signal. Table 11 summarizes the serial mode definitions.
Table 11. Serial Modes
Mode SCLK* SDO* 0 1 2 3 0 0 1 1 0 1 0 1 Description FSYNC frames data FSYNC pulse starts data frame Slave mode Reserved
*Note: Pull-up/pull-down states
The digital interface consists of a single synchronous serial link which communicates audio and control data. In slave mode, SCLK is connected only to the pullup/
Rev. 1.1
S i3 00 0
Primary
Secondary
Primary
FSYNC
D15-D1
D0=1 (Software FC Bit) Secondary Update XMT Data
SDI
XMT Data
SDO
RCV Data
Secondary Update
RCV Data
16 SCLKS 128 SCLKs 256 SCLKs
Figure 15. Secondary Request
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 D7 A D D6 D D5 D4 D D D3 D D2 D D1 D0 D D
SDI
0
0
0
A
A
A
A
R/W
SDO
High Z
High Z
Figure 16. Secondary Communication Data Format--Write Cycle
16
Rev. 1.1
SI3000
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 A D7 D0
SDI
0
0
1
A
A
A
A
D7
D6 D
D5 D4 D D
D3 D
D2 D
D1 D0 D D
R/W
SDO
High Z
D
High Z
Figure 17. Secondary Frame Format--Read Cycle
FUP1 MCLK
FPLL1
/N1
8 bits
P D
VCO1
/5 or /10 *
1024 * fs
*Note: See PLL bit in Register 2
/M1
8 bits
Figure 18. Clock Generation Subsystem (PLL)
Clock Generation Subsystem
The SI3000 contains an on-chip clock generator. Using a single MCLK input frequency, the SI3000 can generate all the desired standard modem sample rates, as well as the common 11.025 kHz rate for audio playback. The clock generator consists of a phase-locked loop (PLL1) that achieves the desired sample frequency. Figure 18 illustrates the clock generator. The architecture of the PLL allows for fast lock time on initial start-up, fast lock time when changing modem sample rates and high noise immunity. A large number of MCLK frequencies between 1 MHz and 60 MHz are supported. Programming the Clock Generator As noted in Figure 18, the clock generator must output a clock equal to 1024*Fs, where Fs is the desired sample
rate. The 1024*Fs clock is determined through programming of the following registers:
Register 3 - N1 divider, 8 bits. Register 4 - M1 divider, 8 bits
N1 (register 3) and M1 (register 4) are 8-bit unsigned values. FMCLK is the clock provided to the MCLK pin. Table 12 list several standard crystal rates that could be supplied to MCLK. When programming the registers of the clock generator, the order of register writes is important. For PLL updates, N1 (register 3) must always be written first, immediately followed by a write to M1 (register 4).
Note: The values shown in Table 12 satisfy the equations above. However, when programming the registers for N1 and M1, the value placed in these registers must be one less than the value calculated from the equations.
Rev. 1.1
17
S i3 00 0
Table 12. MCLK Examples for 8 kHz
MCLK (MHz) 1.8432 4.0000 4.0960 5.2800 5.7600 6.1440 8.1920 9.2160 10.0800 10.5600 11.0592 12.288 14.7456 16.0000 18.4320 24.5760 25.8048 33.7600 44.2368 46.0800 47.9232 48.0000 56.0000 59.200 N1 9 25 1 33 9 3 1 9 63 33 27 3 9 25 9 3 63 211 27 9 117 75 175 185 M1 200 256 10 256 64 20 5 40 256 128 100 10 25 64 20 5 100 256 25 8 100 64 128 128
The final design consideration for the clock generator is the update rate of PLL. The following criteria must be satisfied in order for the PLL to remain stable:
F UP1 =F MCLK ( N1 ) 144kHz
Where FUP1 is shown in Figure 18. Setting Generic Sample Rates The above clock generation description focuses on common modem sample rates. The restrictions and equations above still apply; however, a more generic relationship between MCLK and Fs (the desired sample rate) is needed. The following equation describes this relationship:
M1 5 1024 Fs ------- = ------------------------------N1 MCLK
where Fs is the sample frequency, and all other symbols are shown in Figure 18. Knowing the MCLK frequency and desired sample rate the values for the M1 and N1 registers can be determined. When determining these values, remember to consider the range for each register as well as the minimum update rate for the first PLL. The values determined for M1 and N1 must be adjusted by minus one when determining the value written to the respective registers. This is due to internal logic, which adds one to the value stored in the register. This addition allows the user to write a zero value in any of the registers and the effective divide-by is one. A special case occurs when both M1 and N1 are programmed with a zero value. When M1 and N1 are both zero, the PLL is bypassed.
Sleep Mode
The SI3000 supports a low-power sleep mode. Sleep mode is activated by setting the Chip Power Down (CPD) bit in register 1. When the SI3000 is in sleep mode, the MCLK signal may be stopped or remain active, but it must be active before waking up the SI3000. To take the SI3000 out of sleep mode, pulse the reset pin (RESET) low. In summary, the power down/up sequence is as follows:
1. Set the Power Down bit (PDN, register 6, bit 3). 2. MCLK may stay active or stop. 3. Restore MCLK before initiating the power up sequence. 4. Reset the SI3000 using the RESET pin (after MCLK is present). 5. Program the registers to desired settings.
PLL Lock Times The SI3000 changes sample rates very quickly. However, lock time will vary based on the programming of the clock generator. The following relationship describes the boundaries on PLL locking time:
PLL lock time < 1 ms
It is recommended that the PLL be programmed during initialization.
18
Rev. 1.1
SI3000
Loopback Operation
The SI3000 advanced design provides the manufacturer with increased ability to determine system functionality during production line tests, as well as support for end-user diagnostics. Two loopback modes exist for this purpose, allowing increased coverage of system components. The digital loopback1 mode allows an external device to send audio data to the SDI input pin and receive the signal through the SDO output pin. In this mode, the group delay of the digital filters is present. This mode allows testing of the digital filters, DAC, and ADC. To enable this mode, set the DL bit of register 2. The digital loopback2 mode allows an external device to send audio data to the SDI input pin and receive the signal through the SDO output pin. This mode allows testing of the digital filters, but not the ADC and DAC.
Reducing Power-on Pop Noise
To minimize power-on pop during initialization, a waiting period is recommended before powering up the analog output drivers. The waiting period starts when the reset signal to the SI3000 is negated. The wait time required is dependent on the external load. Typically, the load consists of an AC coupling capacitor in series with an equivalent load resistor to ground. The equivalent load resistor can either be a speaker load, or the input resistance of an external amplifier. The rule-of-thumb for the waiting period in msec is derived by C*(12+R). For example, in the case of a 10 F AC coupling capacitor and resistive load of 1.0 k the recommended waiting period is 10*(12+1) = 130 msec. If the analog outputs drive external amplifiers, another factor to consider is the voltage division ratio determined by R/(R+12), where R represents the input resistance of the external amplifier. This ratio must be kept as small as possible. A good target value is R = 1 k. If needed, add a load resistor in parallel with the amplifier input to lower the effective input resistance of the amplifier stage.
Rev. 1.1
19
S i3 00 0
Control Registers
Note: Any register not listed here is reserved and should not be written. Any register bit labelled reserved should be written to zero during writes to the register. Register 0 can be read (always returns 0) and written safely.
Table 13. Register Summary
Register Name 1 2 3 4 5 6 7 8 9 Control 1 Control 2 PLL1 Divide N1 PLL1 Multiply M1 RX Gain Control 1 ADC Volume Control DAC Volume Control Status Report Analog Attenuation SLSC SRSC LOSC LOT SOT LIG LIM RXG TXG Bit 7 SR Bit 6 Bit 5 Bit 4 SPD HPFD Bit 3 LPD PLL Bit 2 HPD DL1 Bit 1 MPD DL2 Bit 0 CPD
Divider N1 Multiplier M1 MCG MCM HIM LOM SLM IIR HOM SRM
20
Rev. 1.1
SI3000
Register 1. Control 1 Bit Name Type D7 SR R/W D6 D5 D4 SPD R/W D3 LPD R/W D2 HPD R/W D1 MPD R/W D0 CPD R/W
Reset settings = 0000_0000 Bit 7 Name SR Software Reset. 1 = Sets all registers to their reset value. 0 = Enables chip for normal operation.
Note: Bit will automatically clear after being set.
Function
6:5 4
Reserved SPD
Read returns zero. Speaker Drive Power Down. 1= Normal operation 0 = Power down left and right speaker drive. Line Drive Power Down. 1 = Normal operation 0 = Power down line driver. Handset Drive Power Down. 1 = Normal operation 0 = Power down handset driver. MIC Bias Power Down. 1 = Power down MIC bias buffer. 0 = Normal operation Chip Power Down. 1 = Puts SI3000 into power down mode. 0 = Normal operation
3
LPD
2
HPD
1
MPD
0
CPD
Rev. 1.1
21
S i3 00 0
Register 2. Control 2 Bit Name Type
Reset Settings = 0000_0000
D7
D6
D5
D4 HPFD R/W
D3 PLL R/W
D2 DL1 R/W
D1 DL2 R/W
D0
Bit 7:5 4
Name Reserved HPFD Read returns zero. High Pass Filter (HPF) Disable. 1 = HPF disabled 0 = HPF enabled
Function
3
PLL
PLL Divide by 10. 1 = Sets final stage of PLL to divide by 10. 0 = Sets final stage of PLL to divide by 5. Digital Loopback. 1 = Enables digital loopback (DAC analog out ADC analog in). 0 = Normal operation Digital Loopback. 1 = Enables digital loopback (DAC one bit ADC one bit). 0 = Normal operation Read returns zero.
2
DL1
1
DL2
0
Reserved
22
Rev. 1.1
SI3000
Register 3. PLL1 Divide N1 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name N1 Function N1. Contains the (value - 1) for determining the output frequency on PLL. D7 D6 D5 D4 D3 D2 D1 D0
Divider N1 R/W
Register 4. PLL1 Multiply M1 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name M1 Function M1. Contains the (value - 1) for determining the output frequency on PLL. D7 D6 D5 D4 D3 D2 D1 D0
Multiplier M1 R/W
Rev. 1.1
23
S i3 00 0
Register 5. RX Gain Control 1 Bit Name Type D7 LIG R/W D6 D5 LIM R/W D4 D3 D2 D1 D0 IIR R/W
MCG R/W
MCM HIM R/W R/W
Reset settings = 0100_0111 Bit 7:6 Name LIG Line in Gain. 11 = 20 dB gain 10 = 10 dB gain 01 = 0 dB gain 00 = Reserved Line in Mute. 1 = Line input muted 0 = Line input goes to mixer MIC Input Gain. 11 = 30 dB gain 10 = 20 dB gain 01 = 10 dB gain 00 = 0 dB gain MIC Input Mute. 1 = Mute MIC input 0 = MIC input goes into mixer. Handset Input Mute. 1 = Mute handset input 0 = Handset input goes into mixer. IIR Enable. 1 = Enables IIR filter 0 = Enables FIR filter Function
5
LIM
4:3
MCG
2
MCM
1
HIM
0
IIR
24
Rev. 1.1
SI3000
Register 6. ADC Volume Control Bit Name Type Reset settings = 0101_1100 Bit 7 6:2 Name Reserved RXG Read returns zero. RX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = -34.5 dB LSB = 1.5 dB Line Out Mute. 0 = Mute 1 = Active Handset Out Mute. 0 = Mute 1 = Active Function D7 D6 D5 D4 RXG R/W D3 D2 D1 D0
LOM HOM R/W R/W
1
LOM
0
HOM
Rev. 1.1
25
S i3 00 0
Register 7. DAC Volume Control Bit Name Type Reset settings = 0101_1100 Bit 7 6:2 Name Reserved TXG Read returns zero. TX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = -34.5 dB LSB = 1.5 dB SPKR_L Mute. 0 = Mute 1 = Active SPKR_R Mute. 0 = Mute 1 = Active Function D7 D6 D5 D4 TXG R/W D3 D2 D1 D0
SLM SRM R/W R/W
1
SLM
0
SRM
26
Rev. 1.1
SI3000
Register 8. Status Report Bit D7 D6 D5 D4 D3 D2 D1 D0
Name SLSC Type R
SRSC LOSC R R
Reset settings = 0000_0000 Bit 7 Name SLSC Function SPK_L Short Circuit. 1 = Indicate short circuit status is detected at left speaker. 0 = Normal mode SPK_R Short Circuit. 1 = Indicate short circuit status is detected at right speaker. 0 = Normal mode Line Out Short Circuit. 1 = Indicate short circuit status is detected at line out. 0 = Normal mode Read returns zero.
6
SRSC
5
LOSC
4:0
Reserved
Register 9. Analog Attenuation Bit Name Type Reset settings = 0000_0000 Bit 7:4 3:2 Name Reserved LOT Read returns zero. Line Out Attenuation. 11 = -18 dB analog attenuation on Line Output. 10 = -12 dB analog attenuation on Line Output. 01 = -6 dB analog attenuation on Line Output. 00 = 0 dB analog attenuation on Line Output. Speaker Out Attenuation. 11 = -18 dB analog attenuation on Speaker Output. 10 = -12 dB analog attenuation on Speaker Output. 01 = -6 dB analog attenuation on Speaker Output. 00 = 0 dB analog attenuation on Speaker Output. Type D7 D6 D5 D4 D3 D2 D1 D0
LOT R/W
SOT R/W
2:0
SOT
Rev. 1.1
27
S i3 00 0
Pin Descriptions: SI3000
SPKRR MBIAS HDST SDI SDO FSYNC MCLK SCLK
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
SPKRL LINEO GND VA VD LINEI MIC RESET
Pin # 1 2 3 4
Pin Name SPKRR MBIAS HDST SDI
Description Speaker Right Output. Analog output capable of driving a 60 load. Microphone bias output. Handset Input/Output. Handset analog input/output. Serial Port Data In. Serial communication and control data that is generated by the SI3000 to the system DSP. Serial Port Data Out. Serial communication data that is provided by the SI3000 to the system DSP. Frame Sync Output. Data framing signal that is used to indicate the start and stop of a communication data frame. Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or DSP. Serial Port Bit Clock Input/Output. Controls the serial data on SDO and latches the data on SDI. This pin is an input in slave mode and an output in master mode. Reset. An active low input that is used to reset all control registers to a defined initialized state. Also used to bring the SI3000 out of sleep mode.
5 6
SDO FSYNC
7 8
MCLK SCLK
9
RESET
10
MIC
MIC Input. Microphone level or line level input. This input contains selectable gain of 0, 10, 20, or 30 dB with a full scale input level of 1 VRMS. Line Input. Line level input with selectable gain of 0, 10, or 20 dB. The full scale input level is 1 VRMS. Digital Supply Voltage. Provides the digital supply voltage to the SI3000. Nominally either 5 or 3.3 V. Analog Supply Voltage. Provides the analog supply voltage to the SI3000. Nominally either 5 or 3.3 V.
11
LINEI
12 13
VD VA
28
Rev. 1.1
SI3000
Pin # 14 15 16 Pin Name GND LINEO SPKRL Description Ground. Connects to the system digital ground. Line Output. Line level analog output with a 1 VRMS full scale output level. Speaker Left Output. Analog output capable of driving a 60 load.
Rev. 1.1
29
S i3 00 0
Ordering Guide
Table 14. Ordering Guide
Part Number SI3000-KS Package 16-pin SOIC Temperature 0C to 70C
30
Rev. 1.1
SI3000
Package Outline
Figure 19 illustrates the package details for the SI3000. Table 15 lists the values for the dimensions shown in the illustration.
Figure 19. 16-pin Small Outline Plastic Package (SOIC)
Table 15. Package Diagram Dimensions
Controlling Dimension: MM Symbol Min A A1 A2 b c D E e H L L1 0.053 0.004 0.051 0.013 0.007 0.386 0.150 0.050 BSC 0.228 0.016 0.042 BSC -- 0 Inches Max 0.069 0.010 0.059 0.020 0.010 0.394 0.157 -- 0.244 0.050 -- 0.004 8 Millimeters Min 1.35 0.10 1.30 0.330 0.19 9.80 3.80 1.27 BSC 5.80 0.40 1.07 BSC -- 0 Max 1.75 0.25 1.50 0.51 0.25 10.01 4.00 -- 6.20 1.27 -- 0.10 8
Rev. 1.1
31
S i3 00 0
Document Changes from Revision 1.0 to Revision 1.1
! ! ! ! !
Updated Functional Block Diagram. Removed all B-grade references. Updated Table 4 (AC Characteristics). Updated Figure 14. Removed analog loopback feature description.
32
Rev. 1.1
SI3000 NOT E S :
Rev. 1.1
33
S i3 00 0 NOT E S :
34
Rev. 1.1
SI3000 NOT E S :
Rev. 1.1
35
S i3 00 0
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
36
Rev. 1.1

▲Up To Search▲

Price & Availability of SI3000

	To Download SI3000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .